Dielectrically isolated integrated circuits (DI) have long been fabricated in a series of chemical and mechanical process steps resulting in single crystal silicon islands or tubs. These islands or tubs are surrounded on the sides and bottom by a dielectric material such as silicon dioxide and further contained in a matrix of polycrystalline silicon, as illustrated in FIG. 10. The process steps of forming a DI structure is highlighted by anisotropically etching grooves or moats into a polished slice of single crystal silicon, oxidizing the resulting surface, depositing polycrystalline silicon on the surface to a depth dictated by that needed for the final DI slice thickness, then grinding and polishing the original substrate away until the oxidized moat bottoms are exposed and the final required isolated island depth is reached.
The thick polycrystalline deposition step is, however, a primary limiter of the quality and utility of the final DI structure. This is a result of both the thickness and the high temperature deposition required for depositing the polycrystalline material. The high temperature deposition induces warpage on the device surface such that the warpage adversely affects the subsequent mechanical grind and polishing steps, resulting in adversely affecting the final island depth, size and spacing tolerances. This deposition also induces damaging stress into the final islands, resulting in eventual device leakage. This stress is sufficient enough such that the single crystal actually "shrinks", causing the final islands to be out of position relative to their original masked location. This can further lead to mismatching with subsequent processing masks in the integrated circuit fabrication.
One method of compensating for the potential of varying depth, size, spacing and mismatching of the islands, is to purposefully increase the size and depth of the islands. This increase in size and depth, however, unnecessarily increases the surface area of the islands, and therefore, adversely affects the density on the chip.
The final grind and polishing steps on the surface of the semiconductor structure can also cause deleterious effects on the final semiconductor devices. In addition to the thickness variation inherent with any grinding and polishing step, varying amounts of surface damage will also necessarily result from the grinding of the surface. Although the polishing will remove most of the damage of the surface caused by the grinding, it will not remove all the damage imputed onto the surface. Additionally, residual damage can result from the polish. While a "chemical" silicate gel polish is generally used as the finish, this part of the polish must be minimized or severe "stand up" of the oxide coming to the surface will occur. The breaking off of the dielectric oxide during the final stages of polish can also cause some additional damage on the silicon surface. This surface damage results in the significant decrease in the quality of the devices later formed in the structure.
Another method being pursued for achieving isolation between devices is found in the silicon on insulator (SOI) art. By providing a thin layer of insulation between the substrate and the device forming layer, better isolation can be obtained for the devices formed in the semiconductor structure. This results in increasing speed, decreasing power, and improving transient radiation hardness of the semiconductor devices.
One technique for producing the thin SOI semiconductor structure involves subsurface implanted oxygen followed by an epitaxial or device forming layer grown on the silicon substrate. The implanted oxygen is annealed prior to providing the epitaxial layer so that the portion of silicon above the buried oxide becomes acceptable quality single-crystal silicon. The semiconductor devices are formed in the epitaxial layer with the underlying buried oxide providing isolation between the epitaxial layer and the substrate. This method commonly referred to as SIMOX (separation by implanted oxygen) has limitations, however, in the crystal quality of the semiconductor material over the buried oxide. This is due to the effect of bombarding the surface of the semiconductor during implantation. The bombardment adversely affects the crystallization of the semiconductor surface.
An alternative method for forming silicon on insulator structures has evolved in which wafers are bonded together with one of the wafers subsequently being partially removed. An example of this method is disclosed in an article by Brock, et al, "Fushing of Silicon Wafers", IBM Technical Disclosure Bulletin, Vol. 19, No. 9, Feb. 1977, pps. 3405-3406, in which it is stated that "wafers may be fused together conveniently by forming a layer of silicon dioxide on each wafer, then placing the layers of silicon dioxide abutting each other, and heating, preferably in a steamed atmosphere at a temperature in the order of 1050.degree. C. for about one-half hour." One of the wafers is then partially removed, leaving behind a thin layer on the remaining wafer with an oxide therebetween. The resulting SOI wafer can then be made fully dielectrically isolated with sidewall isolation, by etching grooves to the buried oxide and then filling these grovoes with polycrystalline silicon.
The removal of the original substrate in this SOI process, however, involves grinding and polishing the semiconductor surface. This results in similar adverse effects that the grinding and polishing cause in the formation of the previously discussed DI structure.